Microfluidic Very Large Scale Integration (VLSI)
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Microfluidic Very Large Scale Integration (VLSI)
Modeling, Simulation, Testing, Compilation and Physical Synthesis
Madsen, Jan; Pop, Paul; Minhass, Wajid Hassan
Springer International Publishing AG
03/2018
270
Mole
Inglês
9783319806051
15 a 20 dias
454
Descrição não disponível.
Introduction.- Part 1. Preliminaries.- Design Methodology
for Flow-based Microfluidic Biochips.- Biochip Architecture Model.- Biochemical
Application Modeling.- Part 2. Compilation.- Compiling High-Level Languages.- Application
Mapping and Simulation.- Control Synthesis and Pin-Count Minimization.- Part 3.
Physical Design.- Allocation and Schematic Design.- Placement and Routing.- On-Chip
Control Synthesis.- Testing and Fault-Tolerant Design.
for Flow-based Microfluidic Biochips.- Biochip Architecture Model.- Biochemical
Application Modeling.- Part 2. Compilation.- Compiling High-Level Languages.- Application
Mapping and Simulation.- Control Synthesis and Pin-Count Minimization.- Part 3.
Physical Design.- Allocation and Schematic Design.- Placement and Routing.- On-Chip
Control Synthesis.- Testing and Fault-Tolerant Design.
Este título pertence ao(s) assunto(s) indicados(s). Para ver outros títulos clique no assunto desejado.
Biochip Architecture;Biochip Compilation and Synthesis;Biochips;Digital Microfluidic Biochips;Fault-tolerant Biochips;mVLSI Biochips
Introduction.- Part 1. Preliminaries.- Design Methodology
for Flow-based Microfluidic Biochips.- Biochip Architecture Model.- Biochemical
Application Modeling.- Part 2. Compilation.- Compiling High-Level Languages.- Application
Mapping and Simulation.- Control Synthesis and Pin-Count Minimization.- Part 3.
Physical Design.- Allocation and Schematic Design.- Placement and Routing.- On-Chip
Control Synthesis.- Testing and Fault-Tolerant Design.
for Flow-based Microfluidic Biochips.- Biochip Architecture Model.- Biochemical
Application Modeling.- Part 2. Compilation.- Compiling High-Level Languages.- Application
Mapping and Simulation.- Control Synthesis and Pin-Count Minimization.- Part 3.
Physical Design.- Allocation and Schematic Design.- Placement and Routing.- On-Chip
Control Synthesis.- Testing and Fault-Tolerant Design.
Este título pertence ao(s) assunto(s) indicados(s). Para ver outros títulos clique no assunto desejado.