Design Techniques for Mash Continuous-Time Delta-Sigma Modulators
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Design Techniques for Mash Continuous-Time Delta-Sigma Modulators
Briseno-Vidrios, Carlos; Liu, Qiyuan; Edward, Alexander; Silva-Martinez, Jose
Springer International Publishing AG
04/2018
208
Dura
Inglês
9783319772240
15 a 20 dias
506
Descrição não disponível.
Introduction.- Analog-To-Digital and Digital-To-Analog Converters.- Delta-Sigma Modulators.- Design Considerations Of Mash CT-??M.- A 43 mW MASH 2-2 CT ?? Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40nm CMOS.- A 50-MHz BW 67.3-dB SNDR MASH 1-1-1 CT ?? Modulator with FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS.- A 4-Bit Continuous-Time ?? Modulator with Fully Digital Quantizer Noise Reduction Algorithm Employing a 7-bit Quantizer.- Conclusion.
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Analog-To-Digital and Digital-To-Analog Converters;Nanometer CMOS Sigma-Delta Modulators;Delta-Sigma Data Converters;CMOS Cascade Sigma-Delta Modulators;MASH continuous-time delta-sigma modulators
Introduction.- Analog-To-Digital and Digital-To-Analog Converters.- Delta-Sigma Modulators.- Design Considerations Of Mash CT-??M.- A 43 mW MASH 2-2 CT ?? Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40nm CMOS.- A 50-MHz BW 67.3-dB SNDR MASH 1-1-1 CT ?? Modulator with FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS.- A 4-Bit Continuous-Time ?? Modulator with Fully Digital Quantizer Noise Reduction Algorithm Employing a 7-bit Quantizer.- Conclusion.
Este título pertence ao(s) assunto(s) indicados(s). Para ver outros títulos clique no assunto desejado.
